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MB86961A
UNIVERSAL INTERFACE FOR 10BASE -T
DECEMBER 1999 DATASHEET
FEATURES
* * * * * * * * * * * * * * * * * Full-duplex capability Combines Manchester encoder/decoder and twisted pair transceiver functions Direct interface to all popular Ethernet controllers Direct interface to AUI and 10BASE-T outputs Manual or automatic AUI /10BASE-T selection Integrated pulse shaper and Tx/Rx filters Selectable 100 /150 termination permits operation with shielded or unshielded twisted pair cable Reverse-polarity detection for receiver with automatic correction On-chip jabber logic, SQE test and link test with enable/disable option Remote signaling of link down and jabber conditions Programmable receive threshold for extended range Output drivers for receive, transmit, collision and link test pass LED indicators TP loopback enable/disable for external loopback testing Power down mode for minimum power dissipation Automatic shut-down of unused port to reduce power consumption Low power CMOS technology, single 5 volt power supply 44-pin PLCC and 48-pin PQFP packages
polarity reversal on the twisted-pair input. Pulse shaping and filtering functions are performed by the MB86961A to eliminate the need for external filtering components and thus reduce overall system cost. The device also provides outputs for receive, transmit, collision and link test LEDs and provides compatibility with both shielded and unshielded twisted pair cables. The receive threshold can be reduced to allow an extended range between nodes in low noise environments. Its wide range of features and its ability to interface to virtually all popular controllers make the MB86961A the ideal device for twisted pair Ethernet applications. The MB86961A is part of a complete family of Ethernet devices available from Fujitsu. It is fabricated in a lowpower CMOS technology and is supplied in a 44-pin PLCC and 48-pin PQFP packages. PIN CONFIGURATION
65
RLD LI JAB TEST TCLK TXD TEN CLKO CLKI COL AUTOSEL
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
MD1 MD0 NTH CIN CIP VCC1 DON DOP DIN DIP PAUI
4 3 2 1 44 43 42 41 40 39 38 37 36 35
TOP VIEW
34 33 32 31 30 29
TPIN TPIP UTP TPONB TPONA VCC2 GND2 TPOPA TPOPB PLR RJAB
GENERAL DESCRIPTION
The MB86961A Universal Interface for 10BASE-T (Twisted-Pair) Ethernet is fully compliant with the IEEE 802.3 specifications for AUI (Attachment Unit Interface) and 10BASE-T (Twisted-Pair) interfaces and provides the electrical interface between an Ethernet controller and the DB15 (AUI) and RJ45 (10BASE-T) connections to an Ethernet local area network. Functions provided by the MB86961A include Manchester encoding and decoding of the serial data stream, level conversion, collision detection, signal quality error (SQE) and link integrity testing, jabber control, loopback, and automatic correction of
(PLCC Package Shown)
1
LEDR LEDT/PDN LEDL LEDC/XLBK LBK GND1 RBIAS RCMPT RXD CD RCLK
MB86961A
PIN ASSIGNMENT - 44-PIN PLCC PIN
1 2 3 4 5 6 7 8 9 10 11 VCC1 CIP CIN NTH MD0 MD1 RLD LI JAB TEST TCLK -- I I I I I O I O I O
PIN
12 13 14 15 16 17 18 19 20 21 22 TXD TEN CLKO CLKI COL AUTOSEL LEDR LEDT/PDN LEDL LEDC/XLBK LBK I I O I O I O O/I O/I O/I I
PIN
23 24 25 26 27 28 29 30 31 32 33 GND1 RBIAS RCMPT RXD CD RCLK RJAB PLR TPOPB TPOPA GND2 -- I O O O O O O O O --
PIN
34 35 36 37 38 39 40 41 42 43 44 VCC2 TPONA TPONB UTP TPIP TPIN PAUI DIP DIN DOP DON -- O O I I I I I I O O
PIN ASSIGNMENT - 48-PIN PQFP PIN
1 2 3 4 5 6 7 8 9 10 11 12 PAUI DIP DIN DOP DON NC VCC CIP CIN NTH MD0 MD1 I I I O O -- -- I I I I I
PIN
13 14 15 16 17 18 19 20 21 22 23 24 RLD LI JAB TEST TCLK TXD VCC TEN CLKO CLKI COL AUTOSEL O I O I O I -- I O I O I
PIN
25 26 27 28 29 30 31 32 33 34 35 36 LEDR LEDT/PDN LEDL LEDC/XLBK LBK GND NC RBIAS RCMPT RXD CD RCLK O O/I O/I O/I I -- -- I O O O O
PIN
37 38 39 40 41 42 43 44 45 46 47 48 RJAB PLR TPOPB TPOPA GND VCC VCC TPONA TPONB UTP TPIP TPIN O O O O -- -- -- O O I I I
ORDERING CODE PACKAGE STYLE 44-Pin Plastic Leaded Chip Carrier 48-Pin Plastic Quad Flat Package PACKAGE CODE LCC-44P-M02 FPT-48P-M02 VCC = +V + 5% MB86961APD-G MB86961APF-G
2
MB86961A
BLOCK DIAGRAM
PAUI LI LBK Mode Select Logic Controller Compatibility/ Port Select/ Polarity Reverse/ Loopback/Link Test XTAL OSC Manchester Encoder WatchDog Timer DO Collision/ Polarity/ Detect/ Correct Remote Signaling Squelch/ Link Detect Manchester Decoder DI Drop Cable Interface EXL TX AMP LPBK RX Slicer Collision Logic COL CI Collision Receiver DIP DIN CIP CIN DOP DON MD0 MD1 PLS Only PLS/MAU Select UTP Twisted Pair Interface Pulse Shaper & Filter CMOS TX AMP
TCLK CLK1 CLK0 TEN TXD
TPOPB TPOPA TPONA TPONB
RX Slicer
TPIP TPIN
RLD RJAB RCMPT CD LEDL RXD RCLK
LEDT/PDN LEDR
LEDC/XLBK
NTH
JAB
PLR
3
MB86961A
SIGNAL DESCRIPTIONS Symbol AUTOSEL Type I Description AUTOMATIC PORT SELECT: When AUTOSEL=1, automatic port selection is enabled (The MB86981A defaults to the AUI port only if TP link integrity=Fail). When AUTOSEL=0, manual port selection is enabled (the PAUI pin determines the active port). CARRIER DETECT: An output to notify the controller of activity on the network. AUI COLLISION PAIR: Differential input pair connected to the AUI transceiver CI circuit. The input is collision signaling or SQE. CRYSTAL OSCILLATOR: A 20MHz crystal must be connected across these pins, or a 20 MHz clock applied at CLKI. COLLISION DETECT: Output which drives the collision detect input of the controller. AUI RECEIVE PAIR: Differential input pair from the AUI transceiver DI circuit. The input is Manchester encoded. AUI TRANSMIT PAIR: A differential output driver pair for the AUI transceiver cable. The output is Manchester encoded. JABBER INDICATION: Output goes high to indicate Jabber state. LOOPBACK: When LBK=1, forced loopback is enabled. When LBK=0, normal loopback is enabled. COLLISION LED: Open drain driver for the collision indicator. Output is pulled low during collision ( half-duplex mode). If externally tied low, the MB86961A disables the internal TP loopback and collision detection circuits in anticipation of external TP loopback or full-duplex operation. MB86961A is ready for loopback testing 16 ms after this pin goes low. No delay is needed when the pin goes high. LINK LED: Open drain driver for link integrity indicator. Output pulled low during link test pass. If externally tied low, internal circuitry is forced to "Link Pass' state and the MB86961A will continue to transmit link test pulses. RECEIVE LED: Open drain driver for the receive indicator LED. Output is pulled low during receive. TRANSMIT LED/POWER DOWN: Open drain driver for the transmit indicator. Output is pulled low during transmit. If externally tied low, the MB86961A goes to power down state. LINK TEST ENABLE: When LI=0, the Link Integrity Test function is disabled. When LI=1, the Link Integrity Test function is enabled. MODE SELECT: Mode select pins which determine controller compatibility mode. See Table 1. NORMAL THRESHOLD: When NTH=1, the normal TP squelch threshold is in effect. When NTH=0, the normal TP squelch threshold is reduced by 4.5 dB. PORT/AUI SELECT: In Manual Port Select mode (AUTOSEL=0), PAUI selects the active port. When PAUI=1, the AUI port is selected, When PAUI=0, the TP port is selected. In Auto Port Select mode, PAUI is ignored. POLARITY REVERSE: Output goes high to indicate reversed polarity. BIAS CONTROL: A bias resistor at this pin controls the bias of the operating circuit. RECEIVE CLOCK: A recovered 10 MHz clock which is synchronous with the received data and connected to the controller receive clock input.
CD CIP CIN CLKO CLKI COL DIP DIN DOP DON JAB LBK LEDC/XLBK
O I I O I O I I O O O I O/I
LEDL
O/I
LEDR LEDT/ PDN LI MD0 MD1 NTH PAUI
O O/I
I I I I I
PLR RBIAS RCLK
O I O
4
MB86961A
SIGNAL DESCRIPTIONS (Continued) Symbol RCMPT RJAB RLD RXD TCLK TEN TEST TPIP TPIN TPOPA/B TPONA/B Type O O O O O I I O O O O Description REMOTE COMPATIBILITY: Output goes high to signal the controller that the remote port is compatible with the MB86961A remote signaling features. REMOTE JABBER: Output goes high to signal the controller that the remote port is in Jabber condition. REMOTE LINK DOWN: Output goes high to signal to the controller that the remote port is in link down condition. RECEIVE DATA: Output signal connected directly to the receive data input of the controller. TRANSMIT CLOCK: A 10 MHz clock output. This clock signal is directly connected to the transmit clock input of the controller. TRANSMIT ENABLE: Enables data transmission and starts the watchdog timer. Synchronous with TCLK (see Figures 14, 20, 26, and 32 for details). TEST: Input for factory test of the device. Leave open for normal operation. RECEIVE TWISTED-PAIR: A differential input pair from the twisted-pair cable. Receive filter is integrated in-chip. No external filters are required. TRANSMIT TWISTED PAIR: Two differential driver pair outputs (A and B) to the twisted-pair cable. The output is pre-equalized, no external filter is required. Two pairs are used to provide compatibility with both 100 load cable and 150 load cable. TRANSMIT DATA: Input signal containing NRZ data to be transmitted on the network. TXD is connected directly to the transmit data output of the controller. UTP/STP: When UTP=0, 150 termination for shielded TP is selected. When UTP=1,100 termination for unshielded TP is selected. POWER INPUTS: +5V power supply inputs. GROUND RETURNS 1 & 2: Grounds
TXD UTP VCC1, VCC2 GND1 GND2
I I -- -- --
5
MB86961A
APPLICATIONS
Figure 1 shows the MB86961A in a typical application, interfacing between a controller and the RJ45 connector of the twisted-pair network. Figures 2 through 5 show detailed diagrams of various MB86961A applications. external port selection through the PAUI pin. The remote status output are inverted and used to drive LED indicators. (See Figure 3.)
TWISTED-PAIR ONLY
Figure 4 shows the MB86961A is a typical twisted-pair only application. The DTE is connected to a 10BASE-T network through the twisted-pair RJ45 connector. (The AUI port is not used.) With MD0 tied high and MD1 grounded, the MB86961A logic and framing are set to Mode 2 (compatible with Intel 82586 controllers). The LI pin externally controls the link test function. The UTP and NTH pins are both tied low, selecting the reduced receiver threshold and 150 termination for shielded TP cable. The switch at LEDT/PDN manually controls the power down mode. (See Figure 4.)
AUTO PORT SELECT LOOPBACK CONTROL PIN
With MD0 and MD1 both tied high, the MB86961A logic and framing are set to Mode 4 (compatible with National NS8390 controllers). The AUTOSEL pin is tied high, allowing the MB86961A to automatically select the active port. The high at LI enables Link Testing. The UTP and NTH pins are both tied high selecting the standard receiver threshold and 100 termination for unshielded TP cable. (See Figure 2.)
AUI ENCODER/DECODER ONLY
In this application, the DTE is connected to the coaxial network through the AUI. AUTOSEL and PAUI are both tied to ground, manually selecting the AUI port. The twisted-pair port is not used. With MD1 and MD0 both grounded, the MB86961A logic and framing are set to Mode 1 (compatible with AMD AM7990 controllers). The LI pin is tied low, disabling the link test function. The LBK input controls loopback. A 20 MHz crystal connected across CLKI and CLK0 provides the required clock signal. (See Figure 5.)
MANUAL PORT SELECT LINK TEST FUNCTION
With MD0 low and MD1 tied high, the MB86961A logic and framing are set to Mode 3 (compatible with Fujitsu's MB86960 controller). As in Figure 3, the LI pin is tied high, enabling Link Testing, and the UTP and NTH pins are both tied high, selecting the standard receiver threshold and 100 termination for unshielded TP cable. However, in this application AUTOSEL is tied low, allowing
10BASE-T AUI
MB86961A 10BASE-T Inter-
MB86960 Ethernet
H O S B U
Figure 1. Typical System Diagram
6
MB86961A
20 pF
20 MHz
20 pF
1 CLK1 TXD TXE TXC RXC RXD CPS COL +5 V PAUI AUTOSEL MD0 MD1 NTH UTP LI TXD TEN TCLK RCLK RXD CD COL LBK CLK0 TPOPB TPOPA 75 1% 1: 2 37.5 1% 37.5 1% 75 1% 50 1% 0.1F 1:1 1 18pF 2 3 4 5 6 TPIN 50 1% 78 CIN CIP 11 78 DON DOP 330 330 330 330 JAB PLR LEDC/XLBK LEDR LEDL LEDT/PDN VCC1 VCC2 0.1 F DIN DIP 3 78 12 5 13 6 14 7 15 8 D-Connector to AUI Drop Cable 4 2 1 9 2 10 3 Fuse +12 V
RJ45
NS8390 Back-End Controller Interface
TPONA TPONB
To 10Base-T Twisted-Pair Network
Loopback Enable
TPIP
Programming Options
MB86961A
RIAB Remote Status RLD RCMPT
Line Status + 1 F TANT
12.4 K 1% RBIAS GND1 GND2
1 2 3
Suitable crystals includes: MTRON Industries, Inc. MP-1 and MP-2, and Ecliptek ECSM20.000M Suitable TP transformers include: Fil-Mag 23Z128 and SM23Z128, Valor PT4069, and Pulse Engineering PE-65745, PE-65454 and PE-68048 Suitable AUI transformers include: Fil-Mag 23Z90 and SM23Z90, and Valor LT6030
Figure 2. LAN Adapter Board Application - Auto Port Select with External Loopback Control
7
MB86961A
20 pF
20 MHz
20 pF
1 CLK1 TXD TEN TCKN RCKN RXD XCD -XCOL LBC Loopback Enable +5 V Programming Options TXD TEN TCLK RCLK RXD CD COL LBK PAUI AUTOSEL MD0 MD1 NTH UTP LI CLK0 TPOPB TPOPA 75 1% 1: 2 37.5 1% 37.5 1% 75 1% 50 1% TPIP 0.1F 5 6 TPIN 50 1% 78 CIN CIP RIAB RLD Remote Status 330 330 330 330 RCMPT DOP JAB PLR LEDC/XLBK LEDR LEDL LEDT/PDN VCC1 VCC2 0.1 F DIN DIP 3 78 13 6 14 7 15 8 D-Connector to AUI Drop Cable DON 11 78 12 5 4 2 1 9 2 10 3 Fuse +12 V 1:1 1 18pF 2 3 4
RJ45
MB6950 or MB86960 Back-End Controller Interface
TPONA TPONB
To 10Base-T Twisted-Pair Network
330
330
330
MB86961A
Line Status + 1 F TANT
12.4 K 1% RBIAS GND1 GND2
1 2 3
Suitable crystals include: MTRON Industries, Inc. MP-1 and MP-2, and Ecliptek Corp. ECSM20.000M Suitable TP transformers include: Fil-Mag 23Z128 and SM23Z128, Valor PT4069, and Pulse Engineering PE-65745, PE-65454 and PE-68048 Suitable AUI transformers include: Fil-Mag 23Z90 and SM23Z90, and Valor LT6030
Figure 3. LAN Adapter Board Application - Manual Port Select with Link Test Function
8
MB86961A
20 pF
20 MHz
20 pF
1 CLK1 TXD -RTD TXC RXC RXD -CRD -CDT LBK +5 V Programming Options TXD TEN TCLK RCLK RXD CD COL LBK PAUI AUTOSEL MD0 MD1 NTH UTP LI CLK0 TPOPB TPOPA 75 1% 1: 2 37.5 1% 37.5 1% 75 1% 75 1% 0.1F 1:1 1 18pF 2 3 4 5 6 TPIN 75 1% CIN CIP DON DOP DIN DIP 2
RJ45
82586 Back-End Controller Interface
TPONA TPONB
To 10Base-T Twisted-Pair Network
TPIP
Loopback Enable
MB86961A
RIAB Remote Status RLD RCMPT
Line Status 10k 10k 10k
Power Down
Ext. _BK
+ 1 F TANT 0.1 F
JAB PLR LEDC/XLBK LEDR LEDL LEDT/PDN VCC1 VCC2
12.4 K 1% RBIAS GND1 GND2
1 2
Suitable crystals include: MTRON Industries Inc. MP-1 and MP-2, and Ecliptek Corp. ECSM20.000M Suitable TP transformers include: Fil-Mag 23Z128 and SM23Z128, Valor PT4069, and Pulse Engineering PE-65745, PE-65454 and PE-68048
Figure 4. Twisted-Pair Only Application
9
MB86961A
20 pF
20 MHz
20 pF
1 CLK1 TX TENA TCLK RCLK RX RENA CLSN TXD TEN TCLK RCLK RXD CD COL LBK PAUI AUTOSEL MD0 MD1 NTH UTP LI CLK0 TPOPB TPOPA
NS8390 Back-End Controller Interface
TPONA TPONB
Loopback Enable
TPIP
Programming Options
+5 V
TPIN 1 9 2 10 CIP 3 11 78 DON DOP 12 5 13 6 78 14 7 15 DIP 2 8 D-Connector to AUI Drop Cable 4 Fuse +12 V
78 CIN
MB86961A
RJAB Remote Status RLD RCMPT 330 330 330 330
Line Status + 1 F TANT 0.1 F
JAB PLR LEDC/XLBK LEDR LEDL LEDT/PDN VCC1 VCC2
DIN
12.4 K 1% RBIAS GND1 GND2
1 2
Suitable crystals include: MTRON Industries Inc. MP-1 and MP-2, and Ecliptek Corp. ECSM20.000M Suitable AUI transformers include: Fil-Mag 23Z90 and SM23Z90, and Valor LT6030
Figure 5. AUI Encoder/Decoder Only Application
10
MB86961A
FUNCTIONAL DESCRIPTION
The MB86961A Universal Ethernet Interface Transceiver performs the physical layer signaling (PLS) and Media Attachment Unit (MAU) functions as defined by the IEEE 802.3 specification. It functions as a PLS-only device (for use with 10BASE2 or 10BASE5 coaxial cable networks) or as an Integrated PLS/MAU (for use with 10BASE-T twisted-pair networks). The MB86961A interfaces a back-end controller to either an AUI drop cable or twisted-pair (TP) cable. The controller interface includes transmit and receive clock and NRZ data channels, as well as mode control logic and signaling. The AUI interface comprises three circuits: Data output (DO), Data Input (DI) and Collision (CI). The twisted-pair interface comprises two circuits: Twisted-Pair Input (TPI) and Twisted-Pair Output (TPO). In addition to the three basic interfaces, the MB86961A contains an internal crystal oscillator and four LED drivers for visual status reporting. Functions are defined from the back end controller side of the interface. The MB86961A Transmit function refers to data transmitted by the back end to the AUI cable (PLSOnly mode) or to the twisted-pair network (Integrated PLS/MAU mode). The MB86961A Receive function refers to data received by the back end from the AUI cable (PLS-Only) or from the twisted-pair network (Integrated PLS/MAU mode). In the integrated PLS/MAU mode, the MB86961A performs all required MAU functions defined by the IEEE 802.3 10BASE-T specification such as collision detection, link integrity testing, signal quality error messaging, jabber control and loopback. In the PLS-Only mode, the MB86961A receives incoming signals from the AUI DI circuit with up to 18ns of jitter and drives the AUI DO circuit.
CONTROLLER COMPATIBILITY MODES
The MB86961A is compatible with most industry standard controllers including devices produced by Advanced Micro Devices (AMD), Intel, Fujitsu and National Semiconductor. Four different control signal timing and polarity schemes (Modes 1 through 4) are required to achieve this compatibility. Mode select pins MD0 and MD1 determine controller compatibility modes as listed in Table 1.
Table 1.
MD1 0 0
MB86961A Compatibility Modes
Mode Mode 1: Compatible with Advanced Micro Devices AM7990 controllers Compatible with Intel 82586 controllers Compatible with Fujitsu's MB86960 controller Compatible with National Semiconductor 8390 controllers
MD0
0 1 1
1 0 1
Mode 2: Mode 3: Mode 4:
* * * *
Mode 1: Figures 12-17 Mode 2: Figures 18-23 Mode 3: Figures 24-29 Mode 4: Figures 30-35
The related timing specifications are provided in the electrical characteristics section of this data sheet.
11
MB86961A
TRANSMIT FUNCTION
The MB86961A receives NRZ data from the controller at the TXD input (see MB86961A block diagram), and passes it through a Manchester encoder. The encoded data is then transferred to either the AUI cable (the DO circuit) or the twisted-pair network (the TPO circuit). The advanced integrated pulse shaping and filtering network produces the output signal on TPON and TPOP, shown in Figure 6. The TPO output is pre-distorted and prefiltered to meet the 10BASE-T jitter template. No external filters are required. During idle periods, the MB86961A transmits link integrity test pulses on the TPO circuit if LI is enabled and integrated PLS/MAU mode is selected. The MB86961A can be programmed for either shielded TP (150 ) or unshielded TP (100 ) through the UTP pin. decoder and output as decoded NRZ data and receive timing on the RXD and RCLK pins, respectively. No external filters are required. An internal intelligent squelch function discriminates noise from link test pulses and valid data streams. The receive function is activated only by valid data streams above the squelch level and with proper timing. If the differential signal at the TPI or the DI circuit inputs falls below 75% of the threshold level (unsquelched) for eight bit times (typical), the MB86961A receive function enters the idle state. If the polarity of the TPI circuit is reversed, the MB86961A detects the polarity reversal and reports it via the PLR output. The MB86961A automatically corrects reversed polarity.
POLARITY REVERSE FUNCTION JABBER CONTROL FUNCTION
Figure 7 is a state diagram of the MB86961A Jabber control function. The MB86961A on-chip watchdog timer prevents the DTE from locking into a continuous transmit mode. When a transmission exceeds the time limit, the watchdog timer disables the transmit and loopback functions, and activates the JAB pin. Once the MB86961A is in the jabber state, the TXD circuit must remain idle for a period of 0.25 to 0.75 seconds before it will exit the jabber state. The MB86961A polarity reverse function uses both link pulses and end-of-frame data to determine the polarity of the received signal. A reversed polarity condition is detected when eight opposite receive link pulses are detected without receipt of a link pulse of the expected polarity. Reversed polarity is also detected if four frames are received with a reversed start-of-idle. Whenever polarity is reversed, these two counters are reset to zero. If the MB86961A enters the link fail state and no valid
Power On
SQE FUNCTION
NO OUTPUT
In the integrated PLS/MAU mode, the MB86961A supports the signal quality error (SQE) function as shown in Figure 8. After every successful transmission on the 10BASE-T network, the MB86961A transmits the SQE signal to the DTE for 10 5 bit times over the internal CI Circuit.
(DO = Active) NONJABBER OUTPUT Start_XMIT_Max_Timer (DO = Idle) JAB XMIT = Disable LPBK = Disable CI = SQE (DO = Idle) UNJAB WAIT Start_Unjab_Timer XMIT = Disable LPBK = Disable CI = SQE (DO = Active)* (XMIT_Max_Timer_Done)
RECEIVE FUNCTION
The MB86961A receive function acquires timing and data from the twisted-pair network (the TPI circuit) or from the AUI (the DI Circuit). Valid received signals are passed through the on-chip filters and Manchester
(Unjab_Timer_Done)
Figure 6. MB86961A TPO Output Waveform
(DO = Active) (Unjab_Timer_Not_Done)
Figure 7. Jabber Control Function
12
MB86961A
data or link pulses are received within 96 to 128 ms, the polarity is reset to the default non-flipped condition. If Link Integrity Testing is disabled, polarity detection is based only on received data. Polarity correction is always enabled. simultaneous presence of valid signals on both the TPI circuit and the TPO circuit. The MB86961A reports collisions to the back-end via the COL pin. If the TPI circuit becomes active while there is activity on the TPO circuit, the TPI data is passed to the back-end over the RXD circuit, disabling normal loopback. Figure 9 is a state diagram of the MB86961A collision detection function. Refer to Electrical Characteristics for collision detection and COL/CI output timing.
COLLISION DETECTION FUNCTION
The collision detection function operates on the twistedpair side of the interface. A collision is defined as the
Power On
LOOPBACK FUNCTION
The MB86961A provides the normal loopback function specified by the 10BASE-T standard for the twisted-pair port. The loopback function operates in conjunction with the transmit function. Data transmitted by the back-end is internally looped back within the MB86961A from the TXD pin through the Manchester encoder/decoder to the RXD pin and returned to the back-end. The "normal" loopback function is disabled when a data collision occurs, clearing the RXD circuit for the TPI data. Normal loopback is also disabled during link fail and jabber states. The MB86961A also provides additional loopback functions. An external loopback mode, useful for system-level testing, is controlled by pin 21 (LEDC). When LEDC is tied low, the MB86961A disables the collision detection and internal loopback circuits to allow external loopback or full-duplex operation. The MB86961A provides loopback functions controlled by pin 22 (LBK). When the TP port is selected and LBK=1, TP loopback is "forced," overriding collisions on the TP circuit. When LBK=0, normal loopback is in effect.
OUTPUT IDLE
(DO = Active)
OUTPUT DETECTED
(DO = Idle)
SQE WAIT TEST Start_SQE_Test_Wait_Timer (SQE_Test_Wait_Timer_Done)* (XMIT = Enable)
(XMIT = Disable)
SQE TEST Start_XMIT_Max_Timer CI = SQE (SQE_Test_Timer_Done)
Figure 8. SQE Function
A (DO= Active)* (TPI = Idle)* (XMIT = Enabled)
Power On
IDLE
(TPI = Active)
OUTPUT TPO = DO DI = DO
A (DO= Idle) + (XMIT = Disabled) (DO= Active)* (TPI = Idle) (DO= Active)* (TPI = Active)* (XMIT = Enabled) (DO= Active)* (TPI = Active)* (XMIT = Enabled)
INPUT DI = TPI
COLLISION TPO = DO DI = TPI CI = SQE
(DO= Idle)
A (TPI = Idle)
Figure 9. Collision Detection Function
13
MB86961A
When the AUI port is selected and LBK=1, data transmitted by the back-end controller is internally looped back from the TXD pin through the Manchester encoder/decoder to the RXD pin. When LBK=0, no AUI loopback occurs. LINK INTEGRITY TEST Figure 10 is a state diagram of the MB86961A Link Integrity test function. The link integrity test is used to determine the status of the receive side twisted-pair cable. Link integrity testing is enabled when pin 8 (LI) is tied high. When enabled, the receiver recognizes link integrity pulses which are transmitted in the absence of receive traffic. If no serial data stream or link integrity pulses are detected within 50-150 ms, the chip enters a link fail state and disables the transmit and normal loopback functions. The MB86961A ignores any link integrity pulse with an interval less than 2-7 ms. The MB86961A will remain in the link fail state until it detects either a serial data packet or two or more link integrity pulses.
Power On
IDLE TEST Start_Link_Loss_Timer Start_Link_Test_Min_Timer (Link_Loss_Timer_Done) * (TPI = Idle) (Link_Test_Rcvd = False) (TPI = Active) ((Link_Test_Rcvd = True) * (Link_Test_Min_Timer_Done))
LINK TEST FAIL RESET Link_Count = 0 XMIT = Disable RCVR = Disable LPBK= Disable (TPI = Active) (Link_Test_Rcvd = False) * (TPI = Idle)
LINK TEST FAIL WAIT XMIT = Disable RCVR = Disable LPBK= Disable Link_Count = LInk Count + 1
(Link_Test_Rcvd = Idle) * (TPI = Idle)
LINK TEST FAIL Start_Link_Test_Min_Timer Start_Link_Test_Max_Timer XMIT = Disable RCVR = Disable LPBK = Disable (Link_Test_Min_Timer_Done)* (Link_Test_Rcvd = True) LINK TEST FAIL EXTENDED Start_Link_Test_Min_Timer Start_Link_Test_Max_Timer XMIT = Disable (TPI = Idle) * (DO = Idle) (TPI = Idle * Link_Test_Max_Timer_Done) + ((Link_Test_Min_Timer_Done) * (Link_Test_Rcvd = True))
(TPi = Active) + (Link_Count = LC_Max)
Figure 10. Link Integrity Test Function
14
MB86961A
REMOTE SIGNALING The MB86961A transmits standard link pulses which meet the 10BASE-T specification. However, the MB86961A encodes additional status information into the link pulse by varying the link pulse timing. This is referred to as remote signaling. Using alternate pulse intervals, the MB86961A can signal three local conditions: link down, jabber, and remote signaling capability. Figure 11 shows the interval variations used to signal local status to the other end of the line. The MB86961A also recognizes these alternate pulse intervals when received from a remote unit. Remote status conditions are reported to the controller over the RLD, RJAB and RCMPT output pins.
10ms
15ms
20ms
10ms
15ms
20ms
10ms
15ms
20ms
LI-RLD1
20ms
15ms
10ms
20ms
15ms
10ms
20ms
15ms
10ms
LI-RJAB2
10ms LI-RCMPT3
20ms
10ms
20ms
10ms
20ms
10ms
20ms
Notes: 1. For Remote Link Down (RLD) signaling, the interval between LI pulses increments from 10 ms to 15 ms to 20 ms, and then the cycle starts over. 2. For Remote Jabber (RJAB) signaling, the interval between LI pulses decrements from 20 ms to 15 ms to 10 ms, and then the cycle starts over. 3. For Remote Compatibility (RCMPT) signaling, the interval between LI pulses continually switches between 10 ms and 20 ms.
Figure 11. Remote Signaling Link Integrity Pulse Timing
15
MB86961A
ELECTRICAL CHARACTERISTICS
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol VCC TOP TST Supply voltage Operating temperature Storage temperature Rating Conditions Min. -0.3 0 -65 Max. 6 70 150 Units V C C
Note:
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 3. INPUT/OUTPUT CHARACTERISTICS (TA = 0C to +70C, VCC = 5 V 5%)
Symbol VIL VIH VOL Input low Parameter voltage1
2
Condition
Min. -- 2.0
Typ.1 -- -- -- -- -- -- 90 5 3 2 3 2
Max. 0.8 -- 0.4 10 -- -- -- -- -- -- -- --
Units V V V %VCC V %VCC mA mA ns ns ns ns
Input high voltage
Output low voltage
IOL =3.2 mA IOL < 10 mA
-- -- 2.4 90 -- -- -- -- -- --
VOH
Output high voltage
IOH = 40 mA IOH < 10 mA
ICC
Supply current
Normal mode Power-down mode
tR tF
Output rise time
CMOS TTL
TCLK and RCLK TCLK and RCLK TCLK and RCLK TCLK and RCLK
Output fall time
CMOS TTL
Notes: 1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Limited functional test patterns are performed at these input levels. The majority of functional tests are performed at levels 0V and 3 V.
Table 4. AUI ELECTRICAL CHARACTERISTICS (TA = 0C to +70C, VCC = 5 V 5%)
Symbol IIL IIH VOD VDS Parameter Input low current Input high current Differential output voltage Differential squelch threshold Condition Min. -- -- Typ.1 -- -- -- 220 Max. -700 500 Units A A mV mV
550
--
1200
--
Note:
Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
16
MB86961A
Table 5.
Symbol ZOUT VOD tJIT tJIT
TP ELECTRICAL CHARACTERISTICS (TA = 0C to +70C, VCC = 5 V 5%)
Parameter Transmit output impedance Peak differential output voltage Transmit timing jitter addition Transmit timing jitter addition Load=100 at TPOP and TPON 0 line length 1 After line model specified by IEEE 802.3 for 10BASE-T Between TPIP/TPIN, CIP/CIN and DIP/DIN Condition Min. -- -- -- -- Typ.1 5 3.5 -- -- Max. -- -- Units V ns ns
8 3.5
ZIN VDS VDSL
Receive input impedance Differential squelch threshold Lower squelch threshold
-- -- --
20 420 250
-- -- --
k mV mV
Notes: 1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design, not subject to production testing.
Table 6.
Symbol
SWITCHING CHARACTERISTICS (TA = 0C to +70C, VCC = 5 V 5%)
Parameter Condition Min. Typ. Max. Units
Jabber Timing tJAB tUJAB Maximum transmit time Unjab time 20 250 -- -- 150 750 ms ms
Link Integrity Timing tLL tLP1 tLP2 General tRST tTST tLST Receive start-up delay1 Transmit start-up delay1 Loopback start-up delay1 0 0 0 -- -- -- 500 200 500 ns ns ns Time link loss Time between Link Integrity Pulses Interval for valid receive Link integrity Pulses 55 8 4.1 -- -- -- 66 24 65 ms ms ms
Note:
Parameter is guaranteed by design; not subject to production testing.
17
MB86961A
Table 7.
Symbol tDATA tCD tRDS tRDH
RCLK/Start-of-Packet Timing
Parameter Decoder acquisition time AUI TP CD turn-on delay AUI TP Receive data setup from RCLK Mode 1 Modes 2, 3 and 4 Receive data hold from RCLK Mode 1 Modes 2, 3 and 4 Min. -- -- -- -- 40 30 10 30 Typ.1 900 1300 50 400 -- -- -- -- Max. -- -- -- -- -- -- -- -- Units ns ns ns ns ns ns ns ns
Note:
Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
Table 8.
Symbol tRCH tRD tCDOFF tIFG
RCLK/End-of-Packet Timing
Parameter RCLK hold after CD low RCV data throughput delay CD turn off delay Receive block out Type Min. Typ. Typ. Typ. Mode 1 0 300 400 2 Mode 2 1 275 375 50 Mode 3 27 275 375 27 Mode 4 5 275 375 5 Units bt ns ns bt
Notes: 1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CD Turn off delay measured from middle of last bit, so timing specification is unaffected by the value of the last bit.
Table 9.
Symbol tEHCH tDSCH tCHEL tCHDU
Transmit Timing
Parameter TEN setup from TCLK TXD setup from TCLK TEN hold after TCLK TXD hold after TCLK Min. -- -- -- -- Typ.1 30 30 5 5 Max. -- -- -- -- Units ns ns ns ns
Note:
Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
Table 10.
Symbol tCOLD tCOLOFF tSQED tSQEP tKHEH tKHEL
Collision Detection, COL/CI Output and Loopback Timing
Parameter COL turn on delay COL turn off delay SQE Delay SQE Pulse Duration LBK setup from TEN LBK hold after TEN Min. -- -- 0.65 500 -- -- Typ.1 50 160 -- -- 25 0 Max. -- -- 1.6 1500 -- -- Units ns ns ms ns ns ns
Note:
Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
18
MB86961A
MODE 1 (MD1=0, MD0=0) TIMING DIAGRAMS -- FIGURES 12 - 17
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
TPIP/TPIN
tCD CD
RCLK tDATA RXD tRDH tRDS
1
0
1
0
1
0
1
0
1
1
1
0
1
Figure 12. Mode 1 RCLK/SOP Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
tCDOFF CD
tIFG
tRD
RCLK
RXD
1
0
1
0
1
0
1
0
0
Note: RXD is triggered by the rising edge of RCLK, with RCLK advanced by 25 ns. The controller is sampled at the rising edge.
Figure 13. Mode 1 RCLK/EOP Timing
19
MB86961A
TEN tEHCH TCLK tDSCH tCHDU TXD tCHEL
Figure 14. Mode 1 Transmit Timing
CI
tCOLD COL
tCOLOFF
Figure 15. Mode 1 Collision Detect Timing
TEN tSQED COL tSQEP
Figure 16. Mode 1 COL/CI Output Timing
LBK tKHEH TEN tCAEA CD tKHEL
Figure 17. Mode 1 Loopback Timing
20
MB86961A
MODE 2 (MD1=0, MD0=1) TIMING DIAGRAMS -- FIGURES 18 - 23
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
TPIP/TPIN
tCD CD
RCLK tDATA RXD tRDH tRDS
1
0
1
0
1
0
1
0
1
1
1
0
1
Note: RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 18. Mode 2 RCLK/SOP Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
tCDOFF CD tRD RCLK
tIFG
RXD
1
0
1
0
1
0
1
0
0
Note: RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 19. Mode 2 RCLK/EOP Timing
21
MB86961A
TEN tEHCH TCLK tDSCH tCHDU TXD tCHEL
Figure 20.
Mode 2 Transmit Timing
CI
tCOLD COL
tCOLOFF
Figure 21. Mode 2 Collision Detect Timing
TEN t Carrier Detect Blocked tSQED COL tSQEP
Figure 22. Mode 2 COL/CI Output Timing
LBK tKHEH TEN tCAEA CD tKHEL
Figure 23. Mode 2 Loopback Timing
22
MB86961A
MODE 3 (MD1=1, MD0=0) TIMING DIAGRAMS -- FIGURES 24 - 29
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
TPIP/TPIN
tCD CD
RCLK tDATA RXD tRDH tRDS
1
0
1
0
1
0
1
0
1
1
1
0
1
Note: RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 24. Mode 3 RCLK/SOP Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
tCDOFF CD tRD RCLK
tIFG
27 Bits
RXD
1
0
1
0
1
0
1
0
0
Note: RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 25. Mode 3 RCLK/EOP Timing
23
MB86961A
TEN tEHCH TCLK tDSCH tCHDU TXD tCHEL
Figure 26. Mode 3 Transmit Timing
CI
tCOLD COL
tCOLOFF
Figure 27. Mode 3 Collision Detect Timing
TEN tSQED COL tSQEP
Figure 28. Mode 3 COL/CI Output Timing
LBK tKHEH TEN tCAEA CD tKHEL
Figure 29. Mode 3 Loopback Timing
24
MB86961A
MODE 4 (MD1=1, MD0=1) TIMING DIAGRAMS -- FIGURES 30 - 35
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
TPIP/TPIN
tCD CD
RCLK tDATA RXD tRDH tRDS
1
0
1
0
1
0
1
0
1
1
1
0
1
Note: RXD changes at the falling edge of RCLK. The controller is sampled at the rising edge.
Figure 30. Mode 4 RCLK/SOP Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
tCDOFF CD tRD RCLK
tIFG
RXD
1
0
1
0
1
0
1
0
0
Note: RXD changes at the falling edge of RCLK. The controller is sampled at the rising edge.
Figure 31. Mode 4 RCLK/EOP Timing
25
MB86961A
TEN tEHCH TCLK tDSCH tCHDU TXD tCHEL
Figure 32. Mode 4 Transmit Timing
CI
tCOLD COL
tCOLOFF
Figure 33. Mode 4 Collision Detect Timing
TEN tSQED COL tSQEP
Figure 34. Mode 4 COL/CI Output Timing
LBK tKHEH TEN tCAEA CD tKHEL
Figure 35. Mode 4 Loopback Timing
26
MB86961A
44-pin plastic QFJ (PLCC)
(LCC-44P-MO2)
ORDERING INFORMATION: MB86961APD-G
44-pin plastic QFJ (PLCC) (Case No.: LCC-44P-MO2)
17.530.13 SQ (.690.005) 16.590.08 SQ (.653.003)
6 1 44 40
4.30 -0.11 (.169 +.009) -.004 +0.60 2.70 -0.41 +.024 (.106 -.046 ) 0.51(.020)MIN
+0.22
12.70(.500)REF 1.270.13 (050.005)
7
39
0.10(.004) 0.43(.017) TYP 0.66(.026) TYP
INDEX
16.030.51 (.631.020)
17
29
18
28
"A"
Details of "A" part
0.20 -0.02 (.008 +.002) -.001 R0.95(.037)TYP 16.030.51 (.631.020)
+0.05
R0.75(.030) TYP
No.: LEAD No.
(c)1997 FUJITSU LIMITED C44052S-2C-4
Dimension in mm (inches)
27
MB86961A
ORDERING INFORMATION: MB86961APF-G
48-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-48P-M02)
.677.016 SQ
36 25
.106(2.70)MAX .002(0.05)MIN
37
24
.472 +.012 INDEX SQ (12.0 +0.30 )
.535.016 .346(8.80)
13 48
LEAD No.
1
12
.0315(0.80)
.012.002
.006(0.16)
M
.006 +.002 (0.15 +0.05 ) Details of "B" part
Details of "A" part "A" "B" .024(0.60) .006(0.15) .006(0.15) .020(0.50)
0 to 10 .071.012 Dimensions in inches (millimeters)
(c)1992 FUJITSU LIMITED F48002S-9C
28
MB86961A
Worldwide Headquarters
Japan
Tel: Fax:
Fujitsu Limited 1015 Kamiodanaka Nakaharaku Kawasaki 211 Japan
Asia
Tel: Fax:
+81 44 754 3753 +81 44 754 3332
+65 281 0770 +65 281 0220
Fujitsu Microelectronics Asia PTE Limited #05-08, 151 Lorong Chuan New Tech Park Singapore 556741
http://www.fujitsu.co.jp/
http://www.fsl.com.sg/
USA
Tel: Fax:
Europe
Fujitsu Microelectronics Inc 3545 North First Street San Jose CA 95134-1804 USA
+1 408 922 9000 +1 408 922 9179
Tel: +49 6103 6900 Fax: +49 6103 69012
Fujitsu Mikroelektronik GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany
Tel: Fax:
+1 800 866 8608 +1 408 922 9179
Customer Response Center Mon-Fri: 7am-5pm (PST)
http://www.fujitsu.ede.com/
http://www.fujitsumicro.com/
All Right Reserved. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu Microelectronics, Inc. assumes no responsibility for inaccuracies. The information conveyed in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu Limited, its subsidiaries, or Fujitsu Microelectronics, Inc. Fujitsu Microelectronics, Inc. reserves the right to change products or specifications without notice. No part of the publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu Microelectronics, Inc.
LAN-DS-20638-12/97
29

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